//this is the top level of chip
//Last modified by yangjao at 2021/5/10
//bigger15->bigger16 by yjq @ 2021/5/18
module SHA256_SM3_TOP(
    input wire clk,
    input wire rst_n,
    input wire EN,
    input wire select,
    input wire new,
    input wire in_valid,
    input wire [7:0] data_in,

    output wire out_valid,
    output wire[7:0] data_out
);


//----------------------------------------------------------------
// The input module.
//----------------------------------------------------------------
wire Input_W_read, empty;
wire[31:0] W;

Input Input1(
    .clk(clk),
    .rst_n(rst_n),
    .in_valid(in_valid),
    .Input_W_read(Input_W_read),
    .data_in(data_in),

    .empty(empty),
    .W(W)
);

//----------------------------------------------------------------
// The divide module.
//----------------------------------------------------------------

wire[31:0] W_j_7_add_W_j_16;
wire[1:0] S1;
wire W_reg_en, reset;
wire[31:0] W_i;
wire[31:0] W_i_4;
wire[31:0] W_j_7, W_j_16;

Divide Divide1(
    .clk(clk),
    .rst_n(rst_n),
    .W_reg_en(W_reg_en),
    .S(S1),
    .reset(reset),
    .W(W),
    .W_j_7_add_W_j_16(W_j_7_add_W_j_16),

    .W_i(W_i),
    .W_i_4(W_i_4),
    .W_j_7(W_j_7),
    .W_j_16(W_j_16)
);

//----------------------------------------------------------------
// The hash_update module.
//----------------------------------------------------------------

wire hash_reg_en, update, bigger16, bigger32, bigger64;
wire[1:0] S2;

hash_update hash_update1(
    .clk(clk),
    .rst_n(rst_n),
    .hash_reg_en(hash_reg_en),
    .update(update),
    .S(S2),
    .bigger16(bigger16),
    .bigger32(bigger32),
    .bigger64(bigger64),
    .reset(reset),
    .W_i(W_i),
    .W_i_4(W_i_4),
    .W_j_7(W_j_7),
    .W_j_16(W_j_16),

    .hash_Valid(out_valid),
    .data_out(data_out),
    .W_j_7_add_W_j_16(W_j_7_add_W_j_16)
);

control control1(
    .clk(clk),
    .rst_n(rst_n),
    .new(new),
    .in_valid(in_valid),
    .empty(empty),
    .select(select),
    .EN(EN),

    .Input_W_read(Input_W_read),
    .W_reg_en(W_reg_en),
    .hash_reg_en(hash_reg_en),
    .update(update),
    .bigger16(bigger15),
    .bigger32(bigger32),
    .bigger64(bigger64),
    .S1(S1),
    .S2(S2),
    .reset(reset)
);

endmodule